1. Field of the Invention
The present invention relates to an oscillation control circuit.
2. Description of the Related Art
A conventional technique of an oscillation control circuit is known as disclosed, for example, in Japanese patent No. 2585147. This conventional technique is hereinafter described by referring to FIGS. 9-11. FIG. 9 is an electrical circuit diagram showing one example of the conventional technique. FIGS. 10A, 10B, and 10C are a characteristic diagram showing the input/output characteristics (transfer characteristics) of CMOS inverters of FIG. 9. FIG. 11 is a time chart illustrating the operation of FIG. 9.
A CMOS inverter IV8 has input/output characteristics (transfer characteristics) as shown in FIG. 10(A), and has its inversion potential (logical threshold voltage) set at 2.5 volts, for example. The inversion potential referred to herein is an input voltage midway between the fall start input voltage and the fall end input voltage of the input/output characteristics. Normally, it is an input voltage when the output voltage (2.5 V) is half the power-supply voltage (e.g., 5.0 V). A quartz oscillator QZ and a feedback resistor R5 are connected in parallel between the input and output of the CMOS inverter IV8. The input and output terminals are grounded via capacitors C5 and C6, respectively. The CMOS inverter IV8, quartz oscillator QZ, feedback resistor R5, and capacitors C5, C6 together form an oscillator circuit.
A CMOS inverter IV9 has input/output characteristics as shown in FIG. 10B, and has its inversion potential set at 2.0 volts, for example. The input terminal of the CMOS inverter IV9 is connected with the output terminal of the CMOS inverter IV8, while the output terminal is connected with the gate of an N-channel MOS transistor T56. The source of the N-channel MOS transistor T56 is grounded. The drain is connected with one end of a resistor R6, with one end of a capacitor C7, and with the input terminal of a CMOS inverter IV10. The other end of the resistor R6 and the other end of the capacitor C7 are connected with a power supply terminal VDD (5.0 volts). The resistor R6 has a resistance value sufficiently larger than the ON-state resistance value of the MOS transistor T56. The CMOS inverters IV9, IV10, MOS transistor T56, resistor R6, and capacitor C7 described thus far together form an operation control circuit OPC.
The gate of an N-channel MOS transistor T51 is connected with the output terminal of the CMOS inverter IV10. The gate of a P-channel MOS transistor T54 is connected with the output terminal of the CMOS inverter IV10 via a CMOS inverter IV11. The junction of the gates of the N-channel MOS transistor T52 and P-channel MOS transistor T53 is connected with the output terminal of the CMOS inverter IV8. The junction of their drains is connected with a circuit LA at a later stage. The source of the N-channel MOS transistor T52 is grounded via the source/drain of the N-channel MOS transistor T51. The source of the P-channel MOS transistor T53 is connected with the power supply terminal VDD via the source/drain of the P-channel MOS transistor T54. The CMOS inverter IV11, N-channel MOS transistors T51, T52, and P-channel MOS transistors T53, T54 described thus far together form a CMOS clocked inverter. The circuit LA at the later stage is connected with the output of this CMOS clocked inverter.
When the logical output value of the CMOS inverter IV10 is 0, the P-channel MOS transistor T55 shorts out the output from the CMOS inverter formed by the MOS transistors T52 and T53.
The operation of the electric circuit of FIG. 9 is described by referring to FIG. 11. A, B, C, D, and E of FIG. 11 correspond to points a, b, c, d, and e, respectively, of FIG. 9.
As shown in FIG. 11A, when the power supply is turned on, the CMOS inverter IV8 produces an oscillation signal of minute amplitude. Although the amplitude of this oscillation signal increases gradually, the logical output value of the CMOS inverter IV9 is kept at 0 (FIG. 11B) until the oscillation potential drops below the inversion potential (2.0 V) of the CMOS inverter IV9. Therefore, the MOS transistor T56 is driven off. The output of the CMOS inverter IV10 assumes a logical value of 0 (FIG. 11D). As a result, the MOS transistors T51 and T54 are cut off. The CMOS inverter formed by the MOS transistors T52 and T53 is deactivated. At this time, the MOS transistor T55 is ON and so the output from the CMOS inverter formed by the MOS transistors T52 and T53 is shorted out via the MOS transistor T55. In this way, the CMOS inverter formed by the MOS transistors T52 and T53 is maintained in inoperative state until the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 V) of the CMOS inverter IV9. Its logical output value is kept at 1.
When the oscillation potential of the oscillation signal exceeds the inversion potential (2.0 volts) of the CMOS inverter IV9, the output from the CMOS inverter IV9 assumes a logical value of 1 (FIG. 11B), turning on the MOS transistor T56. As a result, as shown in FIG. 11C, the capacitor C7 is charged through the MOS transistor T56. The input voltage to the CMOS inverter IV10 drops rapidly. When the MOS transistor T56 is cut off, electric charge in the capacitor C7 is released via the resistor R6. The input voltage to the CMOS inverter IV10 rises mildly. When the input voltage to the CMOS inverter IV10 drops below its inversion potential, the logical output value of the CMOS inverter IV10 is inverted from 0 to 1. As a result, the CMOS inverter formed by the MOS transistors T52 and T53 is first set into operation. At the same time, the MOS transistor T55 is turned off. By setting the resistance value of the resistor R6 sufficiently greater than the ON-state resistance value of the MOS transistor T56, the logical output value of the CMOS inverter IV10 remains at 1, as shown in FIG. 11D. The oscillation signal generated by the CMOS inverter IV8 is inverted by the CMOS inverter formed by the MOS transistors T52 and T53. As shown in FIG. 11E, a clock signal having a duty cycle of 50% can be produced. This inverted output (clock signal) sets the circuit LA at the later stage into operation.
The circuit at the later stage is set into operation after the amplitude of the oscillation signal reaches a certain magnitude in this way. Consequently, the problem that the oscillation operation is made unstable by the effect of noise produced by the circuit at the later stage to thereby hinder shift from the oscillating operation with minute amplitudes to steady-state amplitude oscillating operation can be solved.
However, it has been required that the oscillator circuit use a higher frequency and consume a less amount of electric power. Therefore, smaller-sized quartz oscillators and lower power-supply voltages have been adopted. With this trend, there is a demand for a decrease in the steady-state amplitude of the oscillation signal. FIG. 12 is a time chart illustrating the operation of the electric circuit of FIG. 9 where the steady-state amplitude of the oscillation signal is suppressed in the conventional case described above. Note that A, B, C, D and E of FIG. 12 correspond to points a, b, c, d, and e, respectively, of FIG. 9.
Since the steady-state amplitude of the oscillation signal is small, the time for which the oscillation potential of the oscillation signal is in excess of the inversion potential (2.0 V) of the CMOS inverter IV9 is shortened as shown in FIG. 12A. Therefore, the time for which the output from the CMOS inverter IV9 assumes a logical value of 1 is shortened and the time for which the output assumes a logical value of 0 is prolonged as shown in FIG. 12B. Consequently, the input voltage to the CMOS inverter IV10 drops rapidly in a shorter time and rises mildly in a longer time. As a result, as shown in FIG. 12C, the input voltage to the CMOS inverter IV10 varies about its inversion potential (2.5 V). Therefore, as shown in FIG. 12D, the logical output value of the CMOS inverter IV10 once makes an inversion from 0 to 1. Immediately thereafter, an inversion from 1 to 0 is made. In this way, unstable state occurs. The oscillation signal produced from the CMOS inverter IV8 is inverted by the CMOS inverter formed by the MOS transistors T52 and T53. The result is that an unstable clock signal is delivered as shown in FIG. 12E.
Where the steady-state amplitude of the oscillation signal is small in this way, the related art technique of FIG. 9 rather suffers from the problem that the clock signal produced to a circuit at a later stage is made unstable.
This may be eliminated by the setting of the charge-discharge time constant of the capacitor C7. However, this adversely affects the operation. In addition, as higher frequency and lower voltage are used, the accuracy presents problems. In this way, problems still exist.
Accordingly, it is an object of the present invention to provide an oscillation control circuit capable of producing a stable clock signal to a circuit at a later stage even if the steady-state amplitude of the oscillation signal is small and of improving the startability of an oscillator circuit that is operated at a high frequency and at a low power-supply voltage.
The present invention provides an oscillation control circuit comprising: a pair of power lines; an oscillator circuit having a first CMOS inverter and a piezoelectric oscillator connected between the output and input terminals of the first CMOS inverter; a second CMOS inverter for receiving an oscillation signal produced from the first CMOS inverter; a control MOS transistor connected between the source of at least one of N- and P-channel transistors forming the second CMOS inverter and at least one of the power lines; and an operation control circuit for maintaining the control MOS transistor in cutoff until the amplitude of the oscillation signal exceeds a given value. The operation control circuit has a capacitor and a Schmitt trigger having input/output characteristics having given hysteresis. The capacitor is charged and discharged according to the oscillation signal. The Schmitt trigger controls the control MOS transistor according to the charging voltage for the capacitor.
An output control circuit may be provided to short the output of the second CMOS transistor to one of the power lines when the control MOS transistor is in cutoff.
The operation control circuit charges the aforementioned capacitor during the period in which the oscillation potential of the oscillation signal is lower than a first reference potential that is lower than the inversion potential of the first CMOS inverter or the oscillation potential of the oscillation signal is higher than a second reference potential that is higher than the inversion potential of the first CMOS inverter. The operation control circuit discharges the capacitor during the remaining period. The output from the Schmitt trigger takes the first logical value when the charging voltage increases beyond a first threshold value. The output from the Schmitt trigger takes the second logical value when the charging voltage drops below a second threshold value that is lower than the first threshold value. The control MOS transistor may be turned ON according to the first logical output value of the output from the Schmitt trigger.
Furthermore, the above-described operation control circuit may discharge the aforementioned capacitor during the period in which the oscillation potential of the oscillation signal is lower than the first reference potential that is lower than the inversion potential of the first CMOS inverter or the oscillation potential of the oscillation signal is higher than the second reference potential that is higher than the inversion potential of the first CMOS inverter. During the remaining period, the operation control circuit charges the capacitor. When the charging voltage drops below the first threshold value, the output from the Schmitt trigger assumes the first logical output value. When the charging voltage increases above the second threshold value that is higher than the first threshold value, the output from the Schmitt trigger takes the second logical output value. The control MOS transistor may be turned ON according to the first logical output value of the output from the Schmitt trigger.